1. Field of the Invention
The present invention relates to a flash EEPROM device enabling a reduced cell size and to a method for fabricating the same.
2. Discussion of the Related Art
Read-only memory (ROM) devices are generally non-volatile memory devices and include programmable ROM (PROM) devices that are electrically programmed after fabrication, mounting, and packaging. In an erasable/programmable ROM (EPROM) device, the programmed data can be erased using ultraviolet light, and in an electrically erasable PROM (EEPROM) device, the programmed data can be erased electrically. A flash memory device, which may be constructed as a NAND or NOR device, is a volatile memory device enabling multiple data rewrite operations electrically.
The programming and erasing of a flash memory device is performed by charging and discharging a floating gate using, for example, channel hot electron injection and Fowler-Nordheim tunneling. In the programming of a memory cell of a flash memory device, such as, a memory cell transistor, a high voltage is applied to the control gate to inject, into the floating gate, electrons from a substrate region near a drain of a memory cell. The transistor's threshold voltage is thereby raised as the injected electrons accumulate in the floating gate. Programming occurs when a predetermined amount of accumulation is reached, such that a logic “1” or a logic “0” is stored in the cell, which can be read by detecting a source-drain current.
After repeated write/erase cycles, the reliability of a flash memory cell becomes degraded over time, and generally deteriorates more quickly in NOR flash devices, according to a deterioration of a tunneling oxide, i.e., a silicon oxide film formed on a source/drain diffusion layer. The deterioration is specifically due to the flow of tunnel current during charging and discharging. In generating tunnel current, a high-voltage electric field (e.g., greater than 8 MV/cm) is applied across the silicon oxide film, creating electron-hole traps in the film and thus facilitating leakage current through the film. This is particularly problematic for a silicon oxide film of 10 nm or thinner.
FIG. 1 illustrates a flash EEPROM device according to a related art. The device comprises a semiconductor substrate 11 in which active and inactive regions are defined by a device isolation film 12; a floating gate 14, formed over the active region, interposing a tunneling oxide film 13; a gate insulating film 15 formed on the floating gate 14; a control gate 16 formed on the gate insulating film 15; sidewall spacers 17 disposed on the lateral sides of each of the floating gate 14 and the control gate 16; source/drain regions 18 formed in a surface of the semiconductor substrate Ion opposite sides of the floating gate 14; an interlayer insulating film 19, formed on an entire surface of the semiconductor substrate 11, in which contact holes are formed to expose pad areas of the source/drain regions 18; and a bit line 20 formed on the interlayer insulating film 19 and connected to the source/drain regions 18 through the contact holes. The above flash EEPROM device has a structure in which two adjacent cells fan out for one bit line contact having a common source line.
Due to a limitation in a design rule, however, there is a limitation in reducing the size of the cell or layout area. The design rule is limited by the bit line contact with the source/drain regions 18. Cell-to-cell isolation requires a device isolation film, which may be formed by shallow-trench isolation or local oxidation of silicon. The device isolation film requires a finite dimension to prevent punch-through, which represents another impediment to cell size reduction. Here, the size of the device isolation film is in general greater than the gate-to-gate design rule.